Sequential logic and counters

Figure 1 shows a system diagram for a timer designed by a student.

The system displays the numbers from 00 to 59 before resetting. The timer is designed to count in time intervals of 1 s.

Part of Figure 1 is enclosed within dashed lines. Figure 2 shows an incomplete circuit diagram for this part of the system. Figure 2 also includes a switch S that is used to manually reset both counters.

Each counter in Figure 2 advances by 1 when CK receives the rising edge of a pulse. When R on a counter receives a logic 1, that counter resets.

Complete the circuit diagram in Figure 2 by adding:

• logic gates to select the reset code for each counter

• a link to show how the second counter is triggered from the first counter

• a resistor with switch S to form the manual reset

• logic gates for each of the counters to provide the reset conditions at R.

Another student designs a logic system to combine judgements from three people. When at least two of the three people input logic 1, the system provides an output of logic 1. Otherwise, the output is logic 0.

The three people are represented by inputs X, Y and Z.

The output Q from this logic system is given by the Boolean expression:

Complete Figure 3 to show the combinational logic diagram for this expression. Use only the logic gates indicated in the expression. Do not transform the expression.

Figure 3

A single logic gate can sometimes be used to replace a more complex logic system.

Figure 4 shows a logic system with inputs A and B and output Q.

Which single logic gate could replace this combinational logic system?

Tick () one box.

A toy manufacturer is designing a two-tone siren for use in small battery-operated cars. Figure 1 shows design Option 1.

Option 1 uses three separate signal generators feeding into a logic sub-system. The signal generators produce logic-compatible 9 V square waves of frequencies 1024 Hz, 1 Hz and 512 Hz.

The waveforms shown are not to scale.

Explain how the logic level applied at B in Figure 1 determines the output frequency at Q.

Write the Boolean algebra expression for output Q in terms of the inputs A, B and C. Use only the logic operations shown in Figure 1.

Option 1 is tested by replacing the 1 Hz signal generator with a manual input.

The manual input is provided by the combination of a push-to-make switch and a 10 kΩ resistor.

The combination produces the following voltages at its output:

• 0 V when the switch is not pressed

• 9 V when the switch is pressed.

Figure 2 shows the symbol for the push-to-make switch.

Figure 2

Complete Figure 3 to show how this switch and the 10 kΩ resistor are connected. Label the output V_out. You do not need to add details taken from Figure 1.

Figure 3

Figure 4 shows a generalised layout of an integrated circuit (IC) for an N-bit binary counter. Q₀ is the output that provides the least significant bit.

A signal generator feeds a square wave of frequency 1024 Hz into the clock of the IC. The N-bit binary counter generates the 512 Hz signal and the 1 Hz signal from separate outputs.

Deduce which of the outputs Q₀ to Q_N will provide the 1 Hz signal.

To make the two-tone siren, the manufacturer decides to use a new design, Option 2

Option 2 contains:

• one 1024 Hz signal generator

• one N-bit binary counter

• a new logic sub-system as shown in Figure 5.

Assume that:

• each type of logic gate has its own dedicated IC chip

• each separate signal generator is based upon its own IC chip.

Compare the number of ICs used in Option 1 with the number used in Option 2. Go on to explain one advantage of the manufacturer’s decision.

Figure 1 shows the input and output pins for a 4-bit binary counter. The output pin for the least significant bit is A.

Complete Figure 1 by adding a single logic gate to the binary counter so that the circuit functions as a modulo-6 counter.

Figure 2 shows three outputs of the modulo-6 counter connected to a logic sub-system that controls a 7-segment display. The decimal point on the display is not shown. The whole system shown in Figure 2 is to be used as an electronic dice.

Segments in the 7-segment display are turned on or off by the logic sub-system to display the decimal numbers 1 to 6 in sequence. A segment in the display turns on when the logic output with the same letter as the segment is at logic 1.

Table 1 shows how the values of CBA control the logic level applied to each of the segments a to g during the counting cycle.

One of the logic outputs a to g is controlled by a single NOT gate. This gate uses one of the inputs A, B or C.

State the input that is used and the segment that this NOT gate controls.

X represents one of the logic outputs. The Boolean expression for this output is:

State which of the logic outputs a to g is being controlled by this function.

Y represents another of the logic outputs. The Boolean expression for this output is:

Complete Figure 3 to show the combination of logic gates needed to represent the expression. You should only use logic gates that represent the individual functions shown in the expression.

Figure 3

A Johnson decade counter uses a Johnson counter together with decoding logic. This arrangement produces a single logic 1 at a series of outputs Q₀–Q₉ in a continuous sequence.

Describe one functional difference and one functional similarity between how a Johnson decade counter and a BCD counter output their counts.

functional difference

functional similarity

An astable oscillator produces a continuous train of pulses. Figure 13 shows the display of the pulses on an oscilloscope.

The oscilloscope settings are:

voltage gain = 2 V / division time-base = 50 µs / division.

Determine the duty cycle and frequency of the signal.

The astable is adjusted to produce a 600 Hz test signal.

This signal is applied to the clock input of the BCD counter and to the clock input of the Johnson decade counter.

The outputs of the BCD counter are Q₀, Q₁, Q₂ and Q₃ where Q₀ is the least significant part of the output. The outputs of the Johnson decade counter are Q₀, Q₁, Q₂…Q₉.

Determine the frequency of the pulses available at Q₂ for each counter.

Figure 1 shows part of a circuit that includes a 4-bit binary counter. The main inputs and outputs of the counter are shown. The counter generates a sequence of binary codes representing the decimal numbers 0 to 7 Output Q₀ is the least significant bit of the binary codes.

The counter resets when the master reset pin MR receives a logic 1

The circuit requires the counter to reset when either one of two conditions is met.

Condition 1 Manual reset using the switch P to reset the counter to 0

Condition 2 Automatic reset when an appropriate binary code is produced at the counter outputs. This will cause the counter to continually cycle through the decimal numbers 0 to 7

Complete Figure 1 to show how both reset conditions can be met.

Do not show the power line connections to the integrated circuit.

A logic system is designed to identify prime numbers.

The binary codes from the counter are now applied to the inputs ABC of the logic system shown in Figure 2.

Input A takes the least significant bit of the binary code from the counter.

Output W becomes logic state 1 when a prime number 2, 3, 5 or 7 is detected. Otherwise output W is at logic 0

Write the Boolean algebra expression for output W in terms of the inputs A, B and C. The expression must contain only the four logic gate operations shown in Figure 2.

Complete Table 1, the truth table for the logic system in Figure 2.

The logic system in Question 01.2 is replaced with one that gives an output S using the same binary input codes CBA.

The Boolean algebra equation for output S is

Deduce which decimal numbers 0 to 7 will cause S to become logic 1

Complete Figure 3 by drawing the logic system for S.

You must use only the logic gate operations given in S = A B.(+ C)

Figure 3

Figure 1 shows the basic layout for a Johnson decade counter. The main input is the clock (CK). The main outputs are shown as Q 0 to Q 9.

Figure 2 shows part of the timing diagram for a Johnson decade counter. This timing diagram shows the output logic states against time. The counter is reset to make Q 0 = 1 and then the first two pulses are applied.

Complete Figure 2 to show the logic states of Q 0, Q 1 and Q 2.

A student sets up the counter to make the traffic light sequence:

red → red + amber → green → amber

The sequence then repeats.

Figure 3 shows a partially completed diagram for producing this sequence.

Draw an OR gate and connections on Figure 3 so that the LEDs go through the complete sequence.

Figure 3

State two factors that determine the ON time for the green LED shown in Figure 3.

The potential difference across the green LED is 2.1 V when it is lit. The current through it should not exceed 9 mA.

All logic gate outputs are: logic low = 0 V logic high = 9 V.

The student suggests that a resistor of resistance 720 Ω and a tolerance of ±5% should be used for R.

Deduce whether the student’s suggestion would be suitable.

A student makes an electronic version of this by feeding pulses from a pulse generator into a 4-bit binary counter.

The circuit uses the first three outputs of the counter A (least significant bit), B and C.

By feeding the outputs from the counter through logic gates, the seven LEDs shown in Figure 4 can be made to display the numbers 1 to 6 in sequence.

Figure 5 shows the sequence of numbers.

The partially completed truth table in Table 1 shows which of the LEDs (L1 to L6) are ON (logic 1) and which are OFF (logic 0) during the counting sequence.

Complete Table 1 to show the logic outputs for the lamps L1 and L6.

Deduce the simplest Boolean expression that can be used to show how output L7 can be controlled by the logic inputs.

Figure 6 shows some of the input and output pins of the 4-bit binary counter.

The data sheet for the counter indicates that the counter resets when the reset pin R is taken from logic 0 to logic 1.

Draw on Figure 6 the logic gate needed and the connections required from the outputs to the reset pin R on the counter so that the counter cycles as required.

The output of both L3 and L4 can be written as (A. B. C) + (B. C)

Figure 7 shows part of a logic circuit needed to represent this Boolean expression.

Complete the logic circuit in Figure 7 by adding AND, OR and NOT gates.